module test;
wire sum,c_out;
reg a,b,c_in;

fulladd  fadd(sum,c_out,a,b,c_in);
/*
initial
begin    
    #15 force fadd.sum=a&b&c_in;
    #20 release fadd.sum;
    
    #10 $stop;    
end
*/
initial
begin
        a=0;b=0;c_in=0;
    #10 a=0;b=0;c_in=1;
    #10 a=0;b=1;c_in=0;
    #10 a=0;b=1;c_in=1;
    #10 a=1;b=0;c_in=0;
    #10 a=1;b=0;c_in=1;
    #10 a=1;b=1;c_in=0;
    #10 a=1;b=1;c_in=1;
    #10 $stop;
end
endmodule